Design an instruction decoder using the gate level constructs and test using Xilinx simulator.

Design and simulate the Behavioral Model for the instruction decoder.

The report should include the Verilog codes screenshots and simulation waveform screenshots for the design. Code should have your name as the engineer and date of creation

Mnemonic	Address mode	Op-code[3:0]	Control[13:0]
LDA	Immediate	0000	00_0000_0000_0001
Memory	1000	00_0001_0000_0000
STA	Memory	0001	00_0000_0000_0010
ADD	Immediate	0010	00_0000_0000_0100
Memory	1010	00_0010_0000_0000
SUB	Immediate	0011	00_0000_0000_1000
Memory	1011	00_0100_0000_0000
MUL	Immediate	0100	00_0000_0001_0000
Memory	1100	00_1000_0000_0000
SWAP	Immediate	0101	00_0000_0010_0000
PAUSE	Immediate	1101	01_0000_0000_0000
JC	Memory	0110	00_0000_0100_0000
JV	Memory	0111	00_0000_1000_0000
JZ	Memory	1111	10_0000_0000_0000

Approach:

a. Generate the truth table for the given inputs and outputs

b. Drawing the K-Maps for the obtained truth tables

c. Gate level Structural Design for the expressions obtained in (b)

d. A test bench for (c)

e. Simulation results for (c)

f. Design the Behavioral model for the expressions obtained in (b)

g. Simulation results for (f) using test bench (d)