Design an One-Hz Clock By Fequency Division Method

This is a Lab using the program Quartus II

Part l Design a circuit and a chip called 'FiveHz Clock

Our DEO board has an on- board clock that produces a 50 MHZ square wave signal. Note: 50MHZ = 5x10^7Hz; To divide this clock to five Hz clock you need to create a counter with MOD 10^7.

Design a circuit to divide the frequency of the on-board clock to an 5 Hz clock: You need to cascade seven decade counter chip 74160 (MOD 10) to generate a counter with total mod: 10x10x10x10x10x10x10=10^7; Set all CLRN and LDN high; set all parallel inputs A, B, C, D low; set first ENT and ENP are connected to the previous chip's RCO; use a single clock trigger all counters; your circuit should have one input called clock, and one output called RCO; create a block symbol (chip) for your circuit.

Part ll Design a circuit and chip called 'OneHz Clock

In the project OneHz_Clock, Design a circuit to truncate a Mod 16 synchronous binary counter 74161 to a Mod 5 counter: Use a NAND gate to clear the counter when the counter generates outputs 0101 = 5; Use AND gate to generate an out put called OneHz which will go high when the counter generates the outputs 0100 = 4. Set the load pin high, and all parallel input pins low.

Use the FiveHz_Clock chip to drive this Mod 5 counter: A single input called Clock is used to connect to the clock pins of both FiveHz_Clock chip and the Mod 5 counter; the output RCO of the FiveHz_Clocl chip is connected to both ENT and Enp of the Mod 5 counter. Your circuit should have one input called Clock, and one output called, OneHz.