Design and draw a sequential circuit having one input $x$ and one output $Y$ that implements the behavior shown in table $1.$ Name inputs and outputs of the

circuit as shown in figure$1($X$,$ RST$,$ clk$,$ Y$).$State S$0$ should be coded as $00.$

Very important note: The VerilUOC$\_$Desktop verifier requires that all inputs of the flip flops are connected to some value. So$,$ it is necessary to connect $"S"$ inputs to

$0$ and "load" inputs to $1.$ To do so$,$ click in "wiring", select "Constant" and connect the constant $($a logical $1)$ to the "load" inputs. Repeat the process and, in the Value

property of the left menu, replace the $0$x$1$ by $0$x$0($this will set the constant to $0).$ Connect the resulting constant to the $"S"$ inputs.

Figure $1$

Table $1$

Instructions to answer this question

In the virtual machine, open VerilUOC$\_$Desktop and draw the circuit.

Click in "Simulate"$->$"Verification" and then click in the VerilCirc tab.

In "Module" select "Graded Exercises" and click on exercise $5\mathrm{.}6.$a$.$

VerilCirc returns a $4$ uppercase letters code. Type it in the answer box.