Design and implement a simple feedforward neural network using Verilog HDL on an FPGA. The network will have one hidden layer and will perform a basic classification task.

Specifications:

$1.$ Network Architecture:

$$ Input Layer: $4$ inputs $($each input is $8-$bit wide$)$

$$ Hidden Layer: $3$ neurons, each with a ReLU activation function.

$$ Output Layer: $2$ outputs $($each output is $8-$bit wide$),$ representing two classes.

$2.$ Weights and Biases:

$$ For simplicity, use $8-$bit signed integers for weights and biases.

$3.$ Activation Function:

$$ Implement the ReLU activation function in Verilog: ReLU$($x$)=$ max$(0,$ x$).$

$4.$ Task:

$$ Implement the feedforward pass of the network, Calculate the outputs of the network for a given input set.