Design and implement the following function using combinatorial digital circuits using gates

and logic components such as multiplexers and decoders.

$($ULO $1)[10$ Marks$]$

$F(a,b,c,d)=b^{\text{'}}{d}^{\text{'}}+c{d}^{\text{'}}+bcd+a{b}^{\text{'}}d+a^{\text{'}}b{d}^{\text{'}}$

A$.$ Design the output K$-$Map

$($ULO $1)[3$ Marks$]$

B$.$ Design the output truth$-$table

$($ULO $1)[3$ Marks$]$

C$.$ Sketch the final design implementation circuit

$($ULO $1)[4$ Marks$]$Analyse the false outputs that could be detected at the output $Z$ from the following state

transition table for the input sequence of $x=10100$ base on the following procedures:

$($ULO $1,2,3,4,5,8)[30$ Marks$]$

$**$ Please note that Part C$,$ D and $E$ are not rely on each others.

Let $Z=x^{\text{'}}{B}^{\text{'}}+xB$

Current State

Next State

Output

A$.$ Determine the outputs on the transition table

$($ULO $3)[5$ Marks$]$

B$.$ Draw the transition graph to identify the sequence of state.

$($ULO $2)[5$ Marks$]$

C$.$ Derive the implement the state transition table with D FF$.$

i$)$ Derive the FF inputs from K$-$Maps

$($ULO $1,2)[2+3$ Marks$]$

ii$)$ Explain your circuit is safe or unsafe

$($ULO $4)[5$ marks$]$

D$.$ Reimplement your design using VHDL instead.

$($ULO $5)[5$ Marks$]$

E$.$ Draw the timing diagram for the $A,B,C,$ and $Z.$ Assuming that the state changes occur on the

rising clock edge and changing $x$ occur between rising and falling clock edges so that the false

outputs can be see. Indicate the false output clearly.

$($ULO $8)[5$ marks$]$