Design Canonical FSM Binary Counter that can count Up & Down

modify the Model for the Four Bit Binary counter in VHDL

You are required to add a new input signal to the FourBitBinaryCounter FSM, so that when the new signal (to which you must give a mnemonically and semantically -significant name (CntDwn_H ???)) is HIGH the counter will count Down, and when the new input signal is LOW, the counter will count Up (if enabled to do so). The Carry-Out signal must be assigned a new meaning of Borrow-Out when the counter is counting down and goes from zero (0000) to fifteen(1111), no new borrow signal needs to be defined just understand the meaning of counting down from (0000) to fifteen (1111) because the counter must generate a borrow to the next more significant Counter stage which should decrement by one.

Then you will write and simulate all relevant test cases for this up/down counter operation on it's two modes of counting. It is suggested that after testing for Resetting the counter, and Loading the counter, then you test for Enabling/Disabling the counter(with or without Carry-In and Count-Enable, and count Up until the Carry-Out is asserted or count down until the Borrow-Out (same signal as Carry-Out) is asserted.

NOTE: For the Simulation you DO NOT have to use the Clock Scaler model, just simulate a clock with a Process() statement in the test bench model and connect it directly to the "BinaryFourBitCounterUsingCanonicalFSM" model under test instance you also created in the test bench.

Four bit counter code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity FourBitCounterFSM is

Port ( CountIn_H : in STD_LOGIC_VECTOR (3 downto 0);

CountOut_H : out STD_LOGIC_VECTOR (3 downto 0);

CarryIn_H : in STD_LOGIC;

CountEn_H : in STD_LOGIC;

CarryOut_H : out STD_LOGIC;

Load_H : in STD_LOGIC;

Rst_L : in STD_LOGIC;

Clk_H : in STD_LOGIC);

end FourBitCounterFSM;

architecture Behavioral of FourBitCounterFSM is

type StateType is (ZeroState, OneState, TwoState, ThreeState, FourState, FiveState, SixState, SevenState,

EightState, NineState, TenState, ElevenState, TwelveState, ThirteenState, FourTeenState, FifteenState);

signal state, next_state : StateType;

begin -- begin of architecture definition

SYNC_PROC: process (Clk_H)

begin

if ( Clk_H'event and Clk_H = '1') then --

if (Rst_L = '0') then

state <= ZeroState;

else

state <= next_state;

end if;

end if;

end process;

OUTPUT_DECODE: process (state, CarryIn_H)

if state = ZeroState then

CountOut_H <= "0000";

CarryOut_H <= '0';

elsif state = OneState then

CountOut_H <= "0001";

CarryOut_H <= '0';

elsif state = TwoState then

CountOut_H <= "0010";

CarryOut_H <= '0';

elsif state = ThreeState then

CountOut_H <= "0011";

CarryOut_H <= '0';

elsif state = FourState then

CountOut_H <= "0100";

CarryOut_H <= '0';

elsif state = FiveState then

CountOut_H <= "0101";

CarryOut_H <= '0';

elsif state = SixState then

CountOut_H <= "0110";

CarryOut_H <= '0';

elsif state = SevenState then

CountOut_H <= "0111";

CarryOut_H <= '0';

elsif state = EightState then

CountOut_H <= "1000";

CarryOut_H <= '0';

elsif state = NineState then

CountOut_H <= "1001";

CarryOut_H <= '0';

elsif state = TenState then

CountOut_H <= "1010";

CarryOut_H <= '0';

elsif state = ElevenState then

CountOut_H <= "1011";

CarryOut_H <= '0';

elsif state = TwelveState then

CountOut_H <= "1100";

CarryOut_H <= '0';

elsif state = ThirteenState then

CountOut_H <= "1101";

CarryOut_H <= '0';

elsif state = FourteenState then

CountOut_H <= "1110";

CarryOut_H <= '0';

elsif state = FifteenState then

CountOut_H <= "1111";

if(CarryIn_H = '1')

then CarryOut_H <= '1';

end if;

else

CountOut_H <= "0000";

CarryOut_H <= '0';

end if;

end process;

NEXT_STATE_DECODE: process (state, Load_H, CarryIn_H, CountEn_H, CountIn_H)

begin

if ( (Load_H = '0') AND (CarryIn_H = '1') AND (CountEn_H = '1') )

then

case (state) is

when ZeroState =>

next_state <= OneState;

when OneState =>

next_state <= TwoState;

when TwoState =>

next_state <= ThreeState;

when ThreeState =>

next_state <= FourState;

when FourState =>

next_state <= FiveState;

when FiveState =>

next_state <= SixState;

when SixState =>

next_state <= SevenState;

when SevenState =>

next_state <= EightState;

when EightState =>

next_state <= NineState;

when NineState =>

next_state <= TenState;

when TenState =>

next_state <= ElevenState;

when ElevenState =>

next_state <= TwelveState;

when TwelveState =>

next_state <= ThirteenState;

when ThirteenState =>

next_state <= FourteenState;

when FourteenState =>

next_state <= FifteenState;

when FifteenState =>

next_state <= ZeroState;

when others =>

next_state <= ZeroState;

end case;

elsif(Load_H = '1')

then

case (CountIn_H) is

when "0000" =>

next_state <= ZeroState;

when "0001" =>

next_state <= OneState;

when "0010" =>

next_state <= TwoState;

when "0011" =>

next_state <= ThreeState;

when "0100" =>

next_state <= FourState;

when "0101" =>

next_state <= FiveState;

when "0110" =>

next_state <= SixState;

when "0111" =>

next_state <= SevenState;

when "1000" =>

next_state <= EightState;

when "1001" =>

next_state <= NineState;

when "1010" =>

next_state <= TenState;

when "1011" =>

next_state <= ElevenState;

when "1100" =>

next_state <= TwelveState;

when "1101" =>

next_state <= ThirteenState;

when "1110" =>

next_state <= FourteenState;

when "1111" =>

next_state <= FifteenState;

when others =>

next_state <= ZeroState;

end case;

end if;

end process;

end Behavioral;