Question: Design in Verilog language Design two digital circuits. The first one will take an n-bit input in 2's complement number format and will give n-bit

Design in Verilog language

Design in Verilog language Design two digital circuits. The first one will take an n-bit input in 2's complement number format and will give

Design two digital circuits. The first one will take an n-bit input in 2's complement number format and will give n-bit output in signed magnitude format. The second one will do the opposite; it takes in n-bit signed magnitude number format and gives out n-bit 2's complement number. The value of n is assumed to be greater than 1

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