Design one stage of a shift register $($e$.$g$.,$ a D$-$type flip$-$flop$)$ using basic gates. This does not have to have a $$Preset$$ function. Construct truth tables and$/$or excitation tables as appropriate and compare these with information in appropriate data sheets of TTL logic units.

The deliverable is a short document $(1-2$ pages$)$ describing the design with appropriate diagrams. Sources of data or information should be acknowledged as references.