Use design procedure to design a sequential circuit that can recognize a bit sequence (S) of following kind S = Bn-1 Bn-2 B2 B1 B0 Where B0 is Least significant bit and Bn-1 is Most significant bit Moreover, S has following characteristics 1- It will contain either count (C) of 0s which is completely divisible by 2. OR 2- Number of 1s in S are multiple of 4 except 0. This circuit will accept a single bit input (X) at each clock pulse and produces a single bit output (Z) accordingly. Sample inputs and outputs of this sequential circuit have also been given on next page, please refer them for more clarification. Note: Use an MN flip flop (as given below) to design this circuit.

Sample input and their corresponding outputs are given as under: Sample 1: Input: 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 0 . Output: 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 . Sample 2: Input: 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 . Output: 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 . Sample 3: Input: 0 1 0 0 0 1 1 0 1 0 1 1 0 1 0 1 . Output: 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 .

a) Draw state diagram for this circuit. b) Find one dimensional state table for state diagram. c) Perform state assignment and draw updated state table. d) Add Flip Flop inputs in state table obtained in part c, also show the updated table. e) Find optimized input equations for all inputs of flip flops by using Kmap, show your whole working (only use updated state table obtained in part d). f) Find optimized output equation for this circuit using K-map, use Boolean algebraic rules/theorems to optimize this equation if more optimization is needed. g) Draw circuit diagram and label it properly, otherwise no credit will be awarded.

Function Table for MIN Flip Flop: Clock M N 0 X O 0 0 O. (M + N). 0 1 1 1 0 0 1 1 Q (M+N) Excitation Table for MIN Flip Flop: Q Q-1 M N 0 0 1 0 0 X 1 0 0 1 1 Function Table for MIN Flip Flop: Clock M N 0 X O 0 0 O. (M + N). 0 1 1 1 0 0 1 1 Q (M+N) Excitation Table for MIN Flip Flop: Q Q-1 M N 0 0 1 0 0 X 1 0 0 1 1