Design Problem

Design a Mealy FSM that recognizes a binary input sequence satisfying the followings

It includes odd number of $1$s

It is an odd number when interpreted as a binary number

It is not an all$-$one sequence.

While drawing Next State Logic and Output Logic circuits in the Mealy FSM Schematic, use three

basic gates only $(2-$input AND gates, $2-$input OR gates, NOT gates$).($For the simplicity of the problem,

we assume we may have an arbitrary output for an empty input sequence!$)$

Grading Criteria:

$100$ points are available for this assignment divided as follows $($no more subdividing, you either get it or not$)$:

State Transition Diagram $(16$ points$)$

Descriptions of States $(10$ points$)$

State Reduction $($if possible$)(6$ points$)$

State Transition & Output Table $(9$ points$)$

State Encoding $(7$ points$)$

State Transition & Output Table with State Codes $(9$ points$)$

K$-$Maps $(10$ points$)$

Simplified Expressions of Next State Bits & Output $(10$ points$)$

Mealy FSM Circuit Schematic

$-$ Next State Logic Circuit $(9$ points$)$

$-$ Output Logic $(7$ points$)$

$-$ Rest of Schematic $(7$ points$)$ Design Problem

Design a Mealy FSM that recognizes a binary input sequence satisfying the followings

$-$ It includes odd number of $1$ s

$-$ It is an odd number when interpreted as a binary number

$-$ It is not an all$-$one sequence.

While drawing Next State Logic and Output Logic circuits in the Mealy FSM Schematic, use three basic gates only $(2-$input AND gates, $2-$input OR gates, NOT gates$).($For the simplicity of the problem, we assume we may have an arbitrary output for an empty input sequence!$)$

Grading Criteria:

$100$ points are available for this assignment divided as follows $($no more subdividing, you either get it or not$)$:

State Transition Diagram

Descriptions of States

State Reduction $($if possible$)$

State Transition $\backslash$& Output Table

State Encoding

State Transition $\backslash$& Output Table with State Codes

K$-$Maps

Simplified Expressions of Next State Bits $\backslash$& Output

Mealy FSM Circuit Schematic

$-$ Next State Logic Circuit

$-$ Output Logic

$-$ Rest of Schematic

$(16$ points$)$

$(10$ points$)$

$(6$ points$)$

$(9$ points$)$

$(7$ points$)$

$(9$ points$)$

$(10$ points$)$

$(10$ points$)$

$(9$ points$)$

$(7$ points$)$

$(7$ points$)$