Design the circuit that multiplies two two$-$bit numbers using $8$x$1$MUX$.$ The design will be made using $8$x$1$MUX $(74151)$integrated and not gate $(7404)$integrated$.$ In the truth table, in the $3$x$3$ case, all outputs will be zero.Simulation images in Proteus and the circuit design with VHDL code will be implemented in the VIVADO environment for simulation.

$1-$ I need the Proteus Design

$2-$ I need VHDL Code