Design the circuit that multiplies two two$-$bit numbers using $8$x$1$ MUX. The design will be made using $8$x$1$ MUX $(74151)$ integrated and not gate $(7404)$ integrated.

Simulation images in Proteus and the circuit design with VHDL code will be implemented in the VIVADO environment for simulation.

The circuit will be tested and simulated using Proteus and VHDL code within the VIVADO environment.

It should include the design stages of the circuit, information about the materials used, truth table, circuit connection and detailed information about the VHDL to be created in Vivado.