a. Design using the VHDL system to model a MOORE finite state machine that acts as a “1011” sequence detector. Your design should detect overlapping sequences. Assume the input is named A, the output is named Z and that an active low reset signal (reset_n) asynchronously resets the machine. Implement positive edge triggered flip-flops.

i. Draw the MOORE model state diagram for the FSM

ii. Write the complete VHDL construct to implement the FSM

b. Write a VHDL description for a 4-bit shift register. The shift register is to be negative edge triggered. Sin is a serial input to the most significant bit of the shift register. Sout is a serial output from the least significant bit of the shift register. En_n is an active low enable. sreg is the 4-bit register. Write only the VHDL ENTITY and ARCHITECTURE construct.

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library ieee use ieeestdlogic1164all entity moorefsm is port ... View the full answer