Determine the (2input) gate count and propagation delay for circuit diagram you found for the previous problem. Use a form similar to the previous homework problem (where tpdNOT = propagation delay of an inverter, tpdAND = propagation delay of a 2input AND gate, and tpdOR = propagation delay of a 2nput OR gate).

/7 Combinational Circuit 2: Dataflow Verilog Descriptiorn le comb_ckt_2 (y, a, b, c, d, input a, b, c, d, e,f; output yi nl, n2, n3, n4, n5; assign nl - (-e & f) & a; assign n2 = e I ~f; assign n3 = e & ~f & c; assign n4 = ~d I ~e ~f; assign n5 = -n2 & b; assign y = n1 I n3 | ~n4 1 n5 ; endmodule