Develop the Top Level to implement for this code in FPGA Kit

The FPGA Kit is ALTERA CYCLONE IV DE-115 EP4CE115F29C7N

Code Verilog :

module alu(DATA1, DATA2, RESULT, SELECT,ZERO);

//initializing the inputs and outputs

input [7:0] DATA1;

input [7:0] DATA2;

input [2:0] SELECT;

output [7:0] RESULT;

output ZERO; reg [7:0] RESULT;

reg ZERO;

reg [7:0] RshiftResult;barrelShifter myRightLogicalShifter(DATA1,DATA2[7:5],RshiftResult);

//creating the always block which runs whenever a input is changed

always @(DATA1,DATA2,SELECT)

begin

//selecting based on the SELECT input using s switch case

case(SELECT)

3'b000:

#1 RESULT = DATA2; //Forward function

3'b001:

#2 RESULT = DATA1 + DATA2; //Add and Sub function

3'b010:

#1 RESULT = DATA1 & DATA2; //AND and Sub function

3'b011:

#1 RESULT = DATA1 | DATA2; //OR and Sub function

//setting 1XX selection inputs.As there are reserved for future references it doesnt matter

//for the time being the output was set to 0 when the select is 1XX

3'b100:

RESULT = RshiftResult;

3'b101:

RESULT = 8'b00000000;

3'b110:

RESULT = 8'b00000000;

3'b111:

RESULT = 8'b00000000;

endcase

end

// creating the ZERO bit using the alu result

//modified part

always@(RESULT)

begin

ZERO = RESULT[0]~|RESULT[1]~|RESULT[2]~|RESULT[3]~|RESULT[4]~|RESULT[5]~|RESULT[6]~|RESULT[7];

end

endmodule

module reg_file(IN, OUT1, OUT2, INADDRESS, OUT1ADDRESS, OUT2ADDRESS, WRITE, CLK, RESET) ;

//Initalizing inputs

input [2:0] INADDRESS;

input [2:0] OUT1ADDRESS;

input [2:0] OUT2ADDRESS;

input WRITE;

input CLK;

input RESET;

input [7:0] IN;

//initializing outputs

output [7:0] OUT1;

output [7:0] OUT2;

//initializing register variablesinteger i;

//creating the register array

reg [7:0] regFile [0:7];

//resetting the registers if the reset is 1 as a level triggered input

always@(*)

if (RESET == 1) begin

#2

for (i = 0; i < 8; i = i + 1)

begin

regFile [i] = 8'b00000000 ;

end

end

//this always block runs of the positive edge of the clock and write to the register if write is ennable

always@(posedge CLK)

begin

if(WRITE == 1'b1 && RESET == 1'b0) begin

#2 regFile [INADDRESS] = IN; //this includes the write reg delay

//$monitor($time, %b,regFile [INADDRESS]);

end

end

//this is for reading the inputs from the registers

//this part was modified after the lab 5 part 3 submission

assign #2 OUT1 = regFile[OUT1ADDRESS];

assign #2 OUT2 = regFile[OUT2ADDRESS];endmodule