Developing digital circuits with specific sequencing requirements demands meticulous design consideration. In this task, design a synchronous, recycling counter using J$-$K flip$-$flops. The counter is tasked with generating the sequence: $0000,0010,0100,0110,1000,1010,1100,1110$ and repeat. The NEXT state for the undesired $($unused$)$ states will be don't cares on the next clock pulse.