$$ Digital Logic Lab $$ Quartus $18$

Timing and clock domain lab:

High Level Overview:

In this lab we will explore the concepts needed to deal with multiple clocks in a design, timing

analysis, and methods for dealing with timing problems.

We will make use of IP $($Intellectual Property$)$ components. IP are functions$/$modules that someone

else has already designed. Much like in software design, in large$-$scale digital designs we do not

write everything we need. In software, this may take the form of libraries, such as the C$++$ standard

template library, or perhaps things like ethernet stacks. Operating systems are another example of

software based IP$.$

The Quartus tool has a lot of IP that it can generate. IP can also be purchased from $3$rd parties, or

found in open$-$source sites such as opencores.org. In Quartus, the built$-$in IP is accessed by means of

the IP Catalog.

In this design, you will go through the steps needed to create a design with multiple clocks, set up

the timing analyzer, build the design and check timing, show methods for improving the timing. This

lab has no $$real$$ purpose other than that but it does closely resemble some of the real world

designs dealing with data streaming and encryption.