Digital Pattern Recognizer (DPR) The following description is about the Digital Pattern Recognizer (DPR), which can be used for comparing two bit-streams where one bit-stream is user data, and the other bit-stream is reference (template) data. Your task is to analyze the following specifications and design the DPR using digital electronic components and logic gates. Figure Q1 depicts the typical view of the DPR User Data Reference Data B DPR Reset Close CLK Figure Q1: Typical view of the DPR Specifications of the DPR 1. The two bit-streams user data and the reference data serially feed to the DPR. 2. User data and reference data are considered equal if three (3) consecutive bit pairs are equal. 3. If two bit-streams are equal for three (3) consecutive clocks, then the output s = user data 4. If two bit-streams are NOT equal, then the output s remains as it is (no change). [01] (i) Draw a truth table for 1-bit magnitude comparator and draw a circuit diagram using logic gates. [5 Marks] Write the structural and behavioural VHDL code for 1-bit magnitude comparator. 15 Marks [Q2] Draw a state diagram for counter that can count up to 4 and produce output when it reaches 4 with a reset option. [5 Marks) Draw a circuit diagram for the counter to represent the state diagram in Q2. [5 Marks) Write the structural or behavioural VHDL code for the counter. 15 Marks] Q3] Draw a state diagram for the DPR. [05 Marks] (11) Draw a circuit diagram by integrating above 1-bit magnitude comparator and the counter with other digital logic components and gates to perform the DPR operation. Clearly explain the working procedure of the DPR, indicating the internal functionality of the pattern recognizer. You must show clearly how the pattern comparison is made according to the given specifications and show the data paths. [10 Marks] Write complete VHDL code for DPR. Clearly show the port mappings of each entity inside DPR. [10 Marks] 24] Briefly explain how you perform functional, and structural testing with the fault model for DPR. [6 Marks] (ii) List commonly used algorithms for testing digital circuits. [4 Marks]