Digital Principles $-$ UFMFF$8-30-1$

Small$-$Scale Project

Design Problem specification:

To design and implement a computer system, central processing unit is considered as the vital component. It has two major components, the control unit, and the arithmetic logic unit $($ALU$).$ You are required to complete the following tasks.

Task $1.$ Design in VHDL and demonstrate on FPGA an $8-$bit ALU circuit that has a $3-$bit select bus $($Select$),8-$bit input data paths $($A $7$:$0$ and $B[7$:$0])$ and $8-$bit output data path $($y$[7$:$0]).$ It should perform the arithmetic and logic operations given in the table $1.$

Table $1$

$\backslash$table$[[$Select$,$Operation,Description$],[000,y=8^{\text{'}}b0,],[001,y=A|B|,$Bitwise OR$],[010,y=A$&$B,$Bitwise AND$],[011,y=A^B,$Bitwise exclusive OR$],[100,y=B,$Bitwise complement$],[101,y=A+B,$Add$],[110,y=A-B,$Subtract$],[111,y=8^{\text{'}}hFF,]]$

Marks$]$

Task $2.$ Derive state table and state diagram for the sequential full adder circuit as illustrated in Figure $1.$ Additionally, implement it using VHDL and verify its simulation log and timing diagram.

$[35$ Marks$]$

Task $3.$ Theoretically analyze and elucidate the conceptual construction of an $8-$bit central processing unit $($CPU$)$ through the utilization of a dataflow block diagram, incorporating taskl and task$2$ as subsystem$5.$ Provide an exploration of additional components necessary for the implementation of your designed CPU.

Marks$]$

The documentation should show justification for any design decisions that you make as well as development logs for both hardware and software. Evidence of approaches used for the co$-$design, co$-$implementation, co$-$testing, co$-$integration, and system integration must be provided.

This assignment will provide experience of the problems and decisions in developing co$-$design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem.

Altera DE$0$ Board:

This board has a Cyclone III FPGA fitted.

Deliverables for Submission

You are required to complete all the tasks and submit in the form of a zip file on Moodle. Please add comments in the code, for better understanding. Marks will be awarded for clarity of description and analysis of adder architectures.

Marking Scheme

Questions

Program Design Approach and Description

Program Design Approach and Description

RTL and Timing waveforms and report

Question $1$ Marks

Program Design Approach and Description

Well commented programs $($including program and fumction bamners$)$

RTL and Timing waveforms and report

Question $2$ Marks

Design Approach and Description Data flow Block: Dingram

$Q^3$

Use of different subsystems and their respective description

Allocated Marks

$10$

$15$

$10$

$35$

$5$

$10$

$10$

$35$

$15$

$15$

$30$