Division is an essential operation in embedded computing systems. In integer division, the relationship between the inputs $($numerator $$ and denominator $)$ and the outputs $($quotient Q and remainder R$)$ can be described as $=+,$ where $,,,$ and $$ are all unsigned integers and $0(1).$ The numerator is also known as dividend, and the denominator is also known as divisor. For background information on integer division, see https:$//$en$.$wikipedia.org$/$wiki$/$Division$\_$algorithm. This project requires you to develop a high$-$speed FPGA design for integer division. $$ The device has three input signals: $$N$,$D$,$ and $$start$.$ Signals $$N$$ and $$D$$ are unsigned integers. The bit$-$width of $$N$$ and $$D$$ is W bits, where W is a parameter specified in the PreLoadFcn function of the Simulink MDL file. W can be set to $8,9,16,20,$ and so on$.$ Signal $$start$$ is a Boolean variable. When signal $$start$$ goes HIGH, calculation should begin. It is assumed that signal $$start$$ will not go HIGH again until calcu