Do b

2. module named minority. It receives three one-bit inputs, a,b, a. (5 points) Write a SystemVeril and c. It produces one one-bit output y that is TRUE if at least two of the inputs are FALSE. madule minory inpust logic a,b,c og output logic ), assign ys va andba and clb and c endmodule b. (5 points) Write a self-checking testbench for this module. You don't need to use a test vector file. Test every possible value of the inputs. module tee+bene