Question: Just need help with number 5, thank you. Write a VHDL module called minority. It receives three inputs a, b, c. It produces one output

Just need help with number 5, thank you.

Write a VHDL module called minority. It receives three inputs a, b, c. It produces one output y, that is TRUE if at least two of the inputs are FALSE. Write an 8:1 multiplexer module called mux8 with inputs S_2:0, d0, d1, d2, d3, d4, d5, d6, d7, and output y

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