Draw a circuit that implements the following VHDL code using gates and D-CE flip-flops:

signal A, B, Q: bit_vector(1 to 2);

----------------------------------

process(CLK)

if CLKevent and CLK = 0 then

if LdA = 1 then Q < A;

elsif LdB = 1 then Q <= B;

end if;

end if;

end process;

Please include a sketch of the circuit; I have an answer that explains the functionality very well, but am still unsure of the actual circuit layout.