Draw a pipeline diagram utilizing the typical 5 stage IF, ID, EX, MEM, WB MIPS designfor the MIPS code below. Also, shade either the left or right side of each stage if it is reading or writing at that specific clock cycle. Draw arrows from the stages where data is made available, directed to where it is needed. Furthermore, list any data hazards encountered in the code (if any).

sub $2, $2, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)