Problem 1 Consider the following assembly language code: 10: add SR3,SR1,SRO; 11: lw SR2,100 (SR3): 12: sub SR9,SR3,SR2 13: add SR4.SRS.SR6; IADD R4 = RS + R6 14: sw SR2,100(SR4) ISTW MEMIR4+100] -R2 IS: addi SR2.SR1,12; 16: beq SR7,SRI.Label: /BEQ R7 RI, Label: 17: lw SR7,120(SR1); Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). ADD R3-R1RO LDW R2-MEMIR3+100] //SUB R9 = R3-R2 //ADDI R2 = R1+ 12; 1: LDW R7- MEMIRI+120]; (a) What is the final execution time of the code? 13 14 IS 16 The final execution time is cycles (b) Verify the number of cycles from part (a). (c) Assuming that the timings for the five pipeline stages are the ones given in the table below, find how long would it take to execute the code in part (a) and the respective speedups: (i) Using a single-cycled processor (i) Using a pipelined processor. ID WB Pipeline Rcgister