Draw the state diagram for the controller specified by the VHDL code below. Specify all state...

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Draw the state diagram for the controller specified by the VHDL code below. Specify all state transition.cenditions and outputs of the controller. (30 Points) 7 1 tbrary IEEE use IEEE.STD LOGIC 1164.ALL entity Controller Circuit1 is Port elk, rat, G, 3 STD LOGIC end Controller Cireuiti echitectuce Behavioral of Controller Ciroultl is type state type is (Start, Sel A. Sel B, Sel C. Ld Reg) signal state 1 atate type :-5tart signal next at state type begin process (elx begin ir rining edge (clk) then if rat 1 then state < atartr eloe next st atate and if and if end proceaa: process (atate, G, H, J) beqin next st <state, case state is when Start- if ((G and H and not J) or (G and H and J) then next at c- Sel Az elaif (inot G and not H and J or (G and not H and 3))-1 ' then next at c Sel B elaif ((not G and not H and not 3) or inot G and H and not 3)) 1 then next et c Bel C end if when Sel A next at c Ld Regz D <1'F next st < Ld Regi when Sel C E -1' noxt st < Ld Reg when Ld Req "> c - 1' next st c Start 1 ' when 1 ' end case end proces end Behaviaral; Draw the state diagram for the controller specified by the VHDL code below. Specify all state transition.cenditions and outputs of the controller. (30 Points) 7 1 tbrary IEEE use IEEE.STD LOGIC 1164.ALL entity Controller Circuit1 is Port elk, rat, G, 3 STD LOGIC end Controller Cireuiti echitectuce Behavioral of Controller Ciroultl is type state type is (Start, Sel A. Sel B, Sel C. Ld Reg) signal state 1 atate type :-5tart signal next at state type begin process (elx begin ir rining edge (clk) then if rat 1 then state < atartr eloe next st atate and if and if end proceaa: process (atate, G, H, J) beqin next st <state, case state is when Start- if ((G and H and not J) or (G and H and J) then next at c- Sel Az elaif (inot G and not H and J or (G and not H and 3))-1 ' then next at c Sel B elaif ((not G and not H and not 3) or inot G and H and not 3)) 1 then next et c Bel C end if when Sel A next at c Ld Regz D <1'F next st < Ld Regi when Sel C E -1' noxt st < Ld Reg when Ld Req "> c - 1' next st c Start 1 ' when 1 ' end case end proces end Behaviaral;

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