Question: Draw the state diagram for the controller specified by the VHDL code below. Specify all state transition.cenditions and outputs of the controller. (30 Points)

Draw the state diagram for the controller specified by the VHDL code

Draw the state diagram for the controller specified by the VHDL code below. Specify all state transition.cenditions and outputs of the controller. (30 Points) 7 1 tbrary IEEE use IEEE.STD LOGIC 1164.ALL entity Controller Circuit1 is Port elk, rat, G, 3 STD LOGIC end Controller Cireuiti echitectuce Behavioral of Controller Ciroultl is type state type is (Start, Sel A. Sel B, Sel C. Ld Reg) signal state 1 atate type :-5tart signal next at state type begin process (elx begin ir rining edge (clk) then if rat 1 then state < atartr eloe next st atate and if and if end proceaa: process (atate, G, H, J) beqin next st

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