During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following...

 

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During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x3=40, x14=24 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address; all values are shown in decimal): 44336 beq x3, x14,80 Write below the value of the bus L1 in decimal: L1 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal: L3 PC >Add Read address Instruction [31-0] Instruction memory Instruction [6-0] L2 Instruction [19-15] Instruction [24-20] Instruction [11-7] Instruction [31-0] Control Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Read Write register data 2 Write data Registers 32 64 Imm Gen Instruction [30,14-12] Shift left 1 L3 MUX Add Sum Zero ALU ALU result ALU control 0 MUX Address Read data Write Data data memory MUXO During a particular clock cycle, consider the CPU shown in the drawing. Assume that the following initial data is present (all values are shown in decimal, DM is Data Memory): x3=40, x14=24 During the cycle in question, assume that the following instruction is executed (the first column is the instruction's address; all values are shown in decimal): 44336 beq x3, x14,80 Write below the value of the bus L1 in decimal: L1 Write below the value of the bus L2 in decimal: L2 Write below the value of the bus L3 in decimal: L3 PC >Add Read address Instruction [31-0] Instruction memory Instruction [6-0] L2 Instruction [19-15] Instruction [24-20] Instruction [11-7] Instruction [31-0] Control Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Read Write register data 2 Write data Registers 32 64 Imm Gen Instruction [30,14-12] Shift left 1 L3 MUX Add Sum Zero ALU ALU result ALU control 0 MUX Address Read data Write Data data memory MUXO

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