Question: ( e ) For the basic processing unit, assume that signals T 1 to T 5 are asserted during the corresponding execution time step. Assume

(e) For the basic processing unit, assume that signals T1 to T5 are asserted
during the corresponding execution time step. Assume that signals Load,
Store, ALU, Call, Return, Branch are asserted based on the instruction being
executed. Write logic expressions for the control signals that are given below.
IR_en =
MEM_write =
(g) Briefly identify the data inputs to the multiplexer that is labelled as MuxY.
(h) Assume that reg. R4 has 08765 and reg. R3 has 04321. Consider the
instruction: Subtract R5, R4, R3. Complete the table for execution of this
instruction, reflecting contents of the internal registers RA, RB, RZ, and RY.
Final contents of reg. R5=
Cycle
( e ) For the basic processing unit, assume that

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