1. Edit the clock divider code included on the next page so that it meets the following three conditions
   1. Slowclock frequency = 1 Hz (or as close as possible)
   2. MediumClock frequency = 2* SlowClock frequency
   3. FastClockFrequency = 2* MediumClock frequencymodify the portions of the code highlighted in red to divide your clock.

entity Clockdivider is port(clk : in std logic; start_timer : in std_logic; FastClock, MediumClock, Slow Clock, ledo : out std_logic); end Clockdivider; architecture behavioral of Clockdivider is begin process variable cnt : std logic vector(x downto 0):="0"; begin wait until ((clk'EVENT) AND (clk = '1')); if (start timer = '1') then cnt := "0"; else cnt :=cnt + 1; end if: FastClock