Please do the question in VHDL

1. Clock divider
   1. Edit the clock divider code included on the next page so that it meets the following three conditions
      1. FastClockFrequency = 2* MediumClock frequency
      2. MediumClock frequency = 2* SlowClock frequency
      3. Slowclock frequency = 1 Hz (or as close as possible)

**This is the CODE TO BE MODIFIED**

entity Clockdivider is

port(clk : in std_logic;

start_timer : in std_logic;

FastClock,MediumClock,SlowClock, led0 : out std_logic);

end Clockdivider;

architecture behavioral of Clockdivider is

begin

process

variable cnt : std_logic_vector(x downto 0):= "0";

begin

wait until ((clk'EVENT) AND (clk = '1'));

if (start_timer = '1') then

cnt := "0";

else

cnt := cnt + 1;

end if;

FastClock <= cnt(a);

MediumClock <= cnt(b);

SlowClock <= cnt(c);

slowClock_sig <= cnt(c);

if (SlowClock_sig = '1') then

led0 <= '1';

else

led0 <= '0';

end if;

end process;

end behavioral;