EE 4375 / 5375: Homework #2: Tiny Processor Undergrads (EE 4375): Implement using Verilog a circuit that accomplishes the following: Implement the Function Unit of Figure 7-9 Show simulation results (Modelsim or ISIM) to prove your design Load enable B select A select A address Write B address o data Load RO R1 MUX N lo 6 R2 R3 0 3 1 2 Decoder Register file B data 1 D address A data Constantin Destination select MB select S MUXB Bus A Bus B X Address Out Data Out External memory and peripherals G select H select B L S20 11 cm Arithmetic/logic unit (ALU) Shifter O H Zero Detect MF select- MUXF Function unit Data in MD select Bus D Fig. 7-9 Block Diagram of a Datapath EE 4375 / 5375: Homework #2: Tiny Processor Undergrads (EE 4375): Implement using Verilog a circuit that accomplishes the following: Implement the Function Unit of Figure 7-9 Show simulation results (Modelsim or ISIM) to prove your design Load enable B select A select A address Write B address o data Load RO R1 MUX N lo 6 R2 R3 0 3 1 2 Decoder Register file B data 1 D address A data Constantin Destination select MB select S MUXB Bus A Bus B X Address Out Data Out External memory and peripherals G select H select B L S20 11 cm Arithmetic/logic unit (ALU) Shifter O H Zero Detect MF select- MUXF Function unit Data in MD select Bus D Fig. 7-9 Block Diagram of a Datapath