Electrical and Computer Engineering Department

Advanced Digital Design

a$.$ Write a behavioral Verilog description for the priority encoder shwon in the figure, with priority of $11$ then $10$ then $12$ then $13.$

b$.$ Write a Verilog description for the Multiplexer.

c$.$ Write a structral description for the System shown in the figure.

d$.$ Derive the truth table of the System shown in the figure, then implement it using two level implementation.

e$.$ Write a testbench that will take instance of part $"c"$ and instance of part $"d"$ above. The system will print "PASS" if they exactly give the same outputs.

f$.$ Intoroduce one error in the truth table, then repeat part $"$ e $".$

g$.$ Use part $"d"$ to write a UDP for the system shown in the figure.