Question: E-Show the timing of the following code sequence in MIPS Integer pipeline assume forwarding, scheduling and branch uses delayed branch and all memory references

E-Show the timing of the following code sequence in MIPS Integer pipeline assume forwarding, scheduling and branch uses delayed branch and all memory references are in cache. MARKS) LOOP: LW R3,0(R1) LW R4, 0(R2) ADD R5, R3, R4 SD R5, 0(R1) ADDI R1, R1, #4 ADDI R2, R2, #4 SUBI R7, R6,R1 (8 BNZ R7, LOOP INSTRUCTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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