exa? please help!!

Complete the behavioral VHDL code of a 4-bit comparator that has two inputs, A and B, 4-bits each and three outputs AeqB, AltB and AgtB, 1 bit each Aeq8 = 1 if A is equal to B else it is equal to 0 AltB = 1 if A is less than B else it is equal to 0 AgtB = 1 if A is greater than B else it is equal to 0 LIBRARY ieee USE ieee.std_logic_1164.all; ENTITY comparator IS PORT( A,B AeqB, AltB, AgtB END comparator ARCHITECTURE Behavior Of comparator IS BEGIN BEGIN AeqB B THEN else END IF END PROCESS END Behavior IN STD_LOGIC IN STD_LOGIC VECTOR (3 DOWNTOO) OUT STD_LOGIC OUT STD_LOGIC_VECTOR (3 DOWNTO 0) BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0) BUFFER STD_LOGIC_VECTOR (3 DOWNTO O) PROCESS (AB) PROCESS(A) PROCESS(B PROCESS (AeqB, AltB. AgtB ) AeqB