0 S. 2 Complete the behavioral VHDL code of a 4-bit comparator that has two inputs, A and B, 4-bits each and three outputs AeqB, AltB and AgtB, 1 bit each. AeqB = 1 if A is equal to B else it is equal to o out of AltB = 1 if A is less than B else it is equal to 0 uestion AgtB = 1 if A is greater than B else it is equal to 0 LIBRARY ieee ; USE ieee.std_logic_1164.all; ENTITY comparator IS PORT ( A, B : AeqB, AltB , AgtB : END comparator; ARCHITECTURE Behavior Of comparator IS BEGIN BEGIN BEGIN AeqB B THEN else END IF; END PROCESS; END Behavior; IN STD LOGIC_VECTOR 3 DOWNTO O) IN STD_LOGIC OUT STD_LOGIC OUT STD LOGIC VECTOR (3 DOWNTO 0) BUFFER STD_LOGIC_VECTOR (3 DOWNTO O) BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0) tart IUEMS vime lel END IF END PROCESS END Behavior, IN STD LOGIC_VECTOR 3 DOWNTO 0) IN STD LOGIC OUT STD LOGIC VECTOR 6 DOWNTO 0) OUT STD LOGIC BUFFER STD LOGIC VECTOR 6 DOWNTO O) BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0) PROCESS (A) PROCESS (A, B) PROCESS AegB, AltB AgtB ) PROCESS (B) AeqB MO AeqB