Question: Exam Problem: Given a C - like code, Inputs: go ( 1 - bit ) Outputs: done ( 1 - bit ) , average (

Exam Problem: Given a C-like code,
Inputs: go (1-bit)
Outputs: done (1-bit), average (8-bit), max(8-bit)
Local Storage: This part is your responsibility and part of this exam. You are also to decide
number of bits that should be used for sum such that an overflow will not occur and average
(the average of all elements in the array) can be correctly calculated.
while(1){
while(!go);
done =0;
max =0;
sum =0;
for(i =0; i <16; i++){
sum = sum + A[i];
temp = A[i];
if (temp > max){
max = temp;
}
if (temp >=100){
A[i]= temp 100;
}
}
average = sum/16;
done =1;
}
1) Draw its HLSM
2) Write Verilog code(s) and testbench to perform both behavioral and post-
synthesis functional simulations of your designed digital system. Use a
clock period of 200ns in the testbench.
Note: If you decide to use a structural way of Verilog code, you must show
and submit work by hand of the designed Datapath and Controller.

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