Example

Consider a $16-$word cache in a processor with a byte$-$addressable memory. A certain program makes repeated sequence of memory word accesses. The memory word addresses $($in hexadecimal$)$ are as follows:

$4044484C7074787C8084888C9094989C048C1014181C20$

Assuming LRU replacement policy for associative caches, determine the miss rates of the program with the following caches:

a$)$ Direct mapped cache, $1$ word$/$block

b$)$ Fully associative cache, $1$ word$/$block

c$)$ Two$-$way set associative cache, $1$ word$/$block

d$)$ Direct mapped cache, $2$ words$/$block

Ignore initial compulsory misses.