executed. Write logic expressions for the control signals that are given below.Question $4$: The Memory System $(22$ marks$)$

$($a$)$ For a $256K4$ SRAM chip, what is the capacity in bits and bytes?

$($f$)$ Derive the address bit breakdown for a direct$-$mapped cache with a capacity

of $64$ kilobytes and a block size of $16$ bytes.

What would be an appropriate organization for the memory$-$cell array?

How are the address inputs used for this chip?

$($b$)$ Give a simple, clear circuit sketch of a DRAM cell with word$/$bit lines labelled.

$($c$)$ Briefly describe how address pins of a DRAM chip are used.

$($d$)$ For block transfers, how is the clock used inside a synchronous DRAM chip?

$($e$)$ What feature in memory chips permits connecting data pins to shared wires?

$($g$)$ In the cache of part $(f)$ above, where does address $0$xC$8$A$460$ map to$?$

$($h$)$ If the cache organization in part $(f)$ is used for a writeback data cache, give

an unsimplified expression for the number of bits of storage in one block.

$($i$)$ Now consider a four$-$way set$-$associative cache organization with $64-$kilobyte

capacity and $16-$byte block size. Provide the address bit breakdown.

$($j$)$ Identify and briefly explain the different types of locality exploited by caches.

IR$\_$en $=$

MEM$\_$write $=$

$($f$)$ The register file has two $32-$bit data outputs. Briefly identify all reg. file inputs.