Exercise $1$

$1-$ What would be the maximal clock frequency of the external trigger signal $($EXTRG$\_$IN $=$ PTB$8)$ of the KL$25\text{'}$s ADC converter if its ADCK clock is selected to be its Bus clock. Assume that the frequency of the bus clock is set to $24$ MHz $.$

$2-$ Provide the proper values of the associated KL$25$ control registers corresponding to the above constraint assuming that:

a$.$ The analog signal is fed to channel $10$ of the KL$25$ ADC module

b$.$ The analog signal is a positive, single ended signal

c$.$ Vref$+(3\mathrm{.}3$ Volts$)$ and vref$-\backslash ((0\backslash$mathrm$\{$~V$\})\backslash )$ are used

d$.$ Number of bits sought in ADCO$\_$RO is $12$ bits