Exercise #$1$:Exercise #$1$: The Fetch$-$Decode$-$Execute Cycle

The purpose of this exerci$\backslash$ The Fetch$-$Decode$-$Execute Cycle

The purpose of this exercise is to test the understanding of the Fetch$-$Decode$-$Execute cycle.

Consider a fictitious and very simplified Von$-$Neumann architecture with:

$5-$bit addresses$/9-$bit values memory

$29-$bit registers for computation named A and B;

$15-$bit Program Counter register;

$19-$bit Current Instruction register;

$11-$bit error register $($set at the end of the cycle$)$ when the execution of an instruction creates an $$error$$ condition.

$6$ instructions: LOAD, STORE, SUBTRACT, JE $($Jump on Error$),$ and STOP $($detailed in the table below$)$

Each instruction is encoded using $9$ bits:

the first $3$ bits give the mnemonics $($or operation code$)$ identifying the instruction $($see table below$)$;

the next bit gives the id of the register that the instruction operates on: $0$ identifying A$,1$ identifying B; and

the last $5$ bits are an operand which can be anything $($e$.$g$.$ an integer number, an address, or even ignored$)$ depending on the instruction.

CPU Instruction Opcode Description

LOAD $010$ Load register value with value from address $($operand$)$

Example: $010110101=010110101$ is executed as $010=$ LOAD, $1=$ B$,$ with the value at address $(10101,$ i$.$e$.$ LOAD B$,[10101].$

For instance, if the memory content at address $10101$ is $11,$ then, at the end of the fetch$-$decode$-$execute cycle, the register B will contain the value $11.$

The value of the error register is not used. It is set to $0$ when this instruction has completed its execution.

STORE $011$ Store register value to address $($operand$)$

Example: $011010101010=011010101$ is executed as $011=$ STORE, $0=$ A$,$ with the value at address $(10101,$ i$.$e$.$ STORE A$,[10101].$

For instance, if the content of the register A is $25$d$,$ then, at the end of the fetch$-$decode$-$execute cycle, the memory location at address $10101$ will contain the value $25.$

The value of the error register is not used. It is set to $0$ when this instruction has completed its execution.

SUB $101$ Subtract register B contents from register A contents. The result is written in A$.$ The error register is set if an underflow happens.

$101000101$: SUB A$,$ B$.$ Note that $6$ bits are ignored

If initially A contains the value $7$ and B $5,$ then, at the end of the fetch$-$decode$-$execute cycle, A will contain $2(=7-5),$ i$.$e$.$ b$00010.$ The error register is set to $0($no error$).$

If initially A contains the value $3$ and B $5,$ then, at the end of the fetch$-$decode$-$execute cycle, A will contain $0($while it should be $"-2"(=3-5)),$ and the error register will be set to $1($signaling the underflow error$)$

The value of the error register is not used for the execution of this instruction.

JE $110$ If the error register value is set to $1,$ set the Program Counter $($PC$)$ value to $($operand$)$ Otherwise, nothing happens $($i$.$e$.$ increment the PC by $1).$ In any case the error register value is set to $0$ at the end of the fetch$-$decode$-$execute cycle

For instance: $110000101$ translates to JE $00101$

Case $1$: If initially the error register is $0$ and the PC value is $11110,$ then at the end of the fetch$-$decode$-$execute cycle, the PC value will be set to $11111$

Case $2$: If initially the error register is $1$ and the PC value is $11110,$ then at the end of the fetch$-$decode$-$execute cycle, the PC value will be set to $00101$

The value of the error register is used for the execution of this instruction.

STOP $111$ Terminates program

For instance: $11100101$ translates to STOP. Note that all bits after the first three ones $(00101$ in this example$)$ are ignored.

The value of the error register is not used for the execution of this instruction.

Part $1$: Warm$-$up

Question $1\mathrm{.}1[2$ points$]$

What does the instruction encoded by $110010001$ do$?$ Show your work.

Question $1\mathrm{.}2[2$ points$]$

Translate $$LOAD A$,[10110]$ to binary. Show your work.

Question $1\mathrm{.}3[2$ point$]$

Among the instruction encodings below, which one is invalid? Give an explanation.

$110101100$

$100110111$

$011110100$

Part $2$: Case study

Assume that initially:

The Program Counter value is set to $12$d$=01100$b; The values of the other registers are undefined.

The memory has the following contents:

Address Contents Address Contents Address Contents Address Contents

$00000101110110010001001100011000001001011111000001001011$

$00001110101001010011100100001000101101011011001101101001$

$00010001111011010100101010101001011100000011010000001011$

$00011100110110010110100000011001100101101011011000000000$

$00100101000110011000100101101010001000110011100100010111$

$00101010011110011010101101111010101010000011101000000100$

$00110100011001011101011000001011000100000111110111101101$

$00111000111011011111100100011011101011110011111100100000$

Question $2\mathrm{.}1[2$ points$]$

What is the address and the first instruction executed by the program? Explain.

Question $2\mathrm{.}2[18$ points$]$

Detail the program execution instruction by instruction $($the program stops after executing the first STOP$).$

Detail what each stage of the Fetch$-$Decode$-$Execute cycl