Exercise 5. [20 Marks] Below is a sequence of references to 16-bit memory word ad 4, 6, 8, 5, 12, 23, 30, 10, 1, 18, 4. 6, 8, 19 (a) [10 Marks] Consider an initially empty, direct-mapped cache with 2-word cache lines and a capacity of 32 bytes. Using the sequence of addresses above, complete the below table describing the cache hits and cache misses resulting from this sequence of references. If the reference results in a cache miss, say which type of cache miss (cold, conflict, capacity) Tag Index Block Offset Hit/MissType of Miss Address 12 23 30 10 18 19 (b) [10 Marks Consider an initially empty, 2-way set associative cache with 2-word cache lines, a capacity of 32 bytes, and an LRU (least recently used) eviction policy. Using the sequence of addresses above, complete the below table describing the cache hits and cache misses resulting from this sequence of references. If the reference results in a cache miss, say which type of cache miss (cold, conflict, capacity) Tag Index Block Offset Hit/Miss Type of Miss 12 23 30 10 18 19