Exercise $6$:

Cache and Memory Performance Evaluation

You are tasked with analyzing the performance of a CPU with the following configuration:

$$Address Space: $32-$bit addresses $(4$GB addressable memory$).$

$$Cache Configuration:

o Cache Size: $512$KB

o Cache Line $($Block$)$Size: $128$bytes

o Cache Associativity: $8-$way set associative

o Write Policy: Write$-$back

o Write Allocation: Write$-$allocate $($on write miss, load the block into the cache$)$

o Replacement Policy: Least Recently Used $($LRU$)$

$$Main Memory: $4$GB of memory.

Part $1$: Cache Organization

$1.$Determine the number of blocks in the cache.

$2.$Determine the number of sets in the cache.

$3.$Determine the number of bits used for the block offset, index, and tag.

Part $2$: Cache Access Sequence

The CPU generates the following sequence of memory accesses $($in hexadecimal$)$:

$0$x$00000000,0$x$00000800,0$x$00001000,0$x$00002000,0$x$00003000,0$x$00004000,0$x$00008000,0$x$00010000,0$x$00020000,0$x$00030000,$

$0$x$00040000,0$x$00050000,0$x$00060000,0$x$00070000,0$x$00080000,0$x$00090000,0$x$000$A$0000,0$x$000$B$0000,0$x$000$C$0000,0$x$000$D$0000$

For each of the memory accesses, determine if it results in a cache hit or a cache miss, and simulate the cache replacement process $($using the LRU policy$).$

Part $3$: Virtual Memory $($Page Table Simulation$)$

Assume that the CPU uses paging for virtual memory with the following configuration:

$$Page Size: $4$KB

$$Virtual Address Space: $32-$bit, so the total virtual memory size is $4$GB$.$

$$Physical Address Space: $32-$bit, so the total physical memory size is also $4$GB$.$

$1.$Determine the number of pages in virtual memory and the number of frames in physical memory.

$2.$Simulate the translation of virtual addresses to physical addresses for each memory access.

Part $4$: Performance Analysis

$1.$Calculate the cache hit ratio and miss penalty based on the cache access sequence.

$2.$Calculate the page fault rate and determine the effective memory access time $($EMAT$)$considering a page fault penalty of $120$cycles$.$

Exercise $3$:

A CPU produces the following sequence of read addresses in hexadecimal:

A$4,78,30,$C$0,7$C$,$F$8,18,$A$4,88,70,18,$D$4,30,7$C

$$The word size is $32$bits$.$

$$Assume an $8-$word cache that is initially empty.

$$Implement a Least Recently Used $($LRU$)$replacement policy.

For each of the following cache types, determine whether each address produces a hit or a miss:

$$Direct Mapping

$$Fully Associative

$$Two$-$way set$-$associative

Task:

$1.$Fill in the table with Address $($Hex$),$Address $($Binary$),$Direct Mapping, Fully Associative, and $2-$Way Set Associative.

$2.$Sketch the cache after processing all addresses and note replacements.

$3.$Compare the hit ratio for each cache type.

$4.$Discuss how changing the cache design to use $2$words per block would affect the hit$/$miss behavior.

$5.$Explain the impact of miss penalty on the system performance.