Exercise 8.1. Dimensionality of data arrays Using figure 8.1 as reference, list the dimension of each signal (s1 to s14) of table 8.3. Write also the number of wires needed to physically implement each signal. scalar 1D 0100 (b) 1Dx 1D 0100 0110 1000 (C) 2D 0 1 0 0 0 1 1 0 10 0 0 (d) 1Dx 10x1D nas ias 0100 0110 1000 (e) Figure 8.1 Data array dimensionality when using "bit" (one wire) as measurement unit. 3D (f) Table 8.3 Exercise 8.1 type typel is array (7 downto 0) of std_logic; type type2 is array (1 to 3) of typel; type type3 is array (1 to 2) of type2; type type4 is array (1 to 3, 7 downto 0) of std_logic; signal s1: bit; signal s2: bit_vector(0 to 4); signal s3: boolean_vector (1 to 8); signal s4: std_logic; signal s5: std_logic_vector (7 downto 0); signal s6: unsigned (7 downto 0); signal s7: signed (5 downto 0); signal s8: ufixed (3 downto -4); signal s9: sfixed (5 downto -4); signal s10: float (4 downto -4); signal s11: type1; signal s12: type2; signal s13: type3; signal s14: type4;