Exercise 8.8 A cache has the following parameters: b, block size given in numbers of words; S, number of sets; N, number of ways; and A, number of address bits. (a) In terms of the parameters described, what is the cache capacity, C? (b) In terms of the parameters described, what is the total number of bits required to store the tags? (c) What are S and N for a fully associative cache of capacity C words with block size b? (d) What is S for a direct mapped cache of size C words and block size b? Exercise 8.9 A 16-word cache has the parameters given in Exercise 8.8. Consider the following repeating sequence of LDR addresses (given in hexadecimal): 40 44 48 4C 70 74 78 7C 80 84 88 8C 90 94 98 9C 0 4 8 C 10 14 18 1C 20 Assuming least recently used (LRU) replacement for associative caches, determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects (i.e., compulsory misses). (a) direct mapped cache, b= 1 word (b) fully associative cache, b = 1 word (c) two-way set associative cache, b = 1 word (d) direct mapped cache, b=2 words