Exercise N3: _(10 points) The figure below presents a 4-bit asynchronous counter based on D flip-flops. DO DO DO clk Cik k 0 cnt(0) De Cik o ent(1) k Q cnt(2) cnt(3) 1- Propose an VHDL Entity of the circuit above (2 points) 2- Propose a VHDL Architecture code for our system. (4 points) 3- Propose a VHDL Testbench code (4 points)