Exercise

Write a right$-$shift SystemVerilog module that shifts the $8-$bit input data $[7$:$0$ right logically by the number of positions specified by the $3-$bit input shift $2$:$0,$ and outputs it on the $8-$bit output shout $7$:$0.$ However, instead of using the shift operator$($assign shout $[7$:$0]=$data$[7$:$0]shift[2$:$0]$;$,$ instead use nested conditional operators and concatenations.

Write a SystemVerilog testbench model that tests your shift module by applying all eight possible shift For each shift value, apply two different dat'a input values, resulting in $16$ total tests. Choose data values that make it easy to see that the result on shout is correctly shifted, and that both $1\text{'}$s and O$\text{'}$s can be shifted.

Simulate the module together with the testbench using Vivado.

Upload the following to Canvas for grading:

All SystemVerilog code that you wrote: functional module and testbench. The SystemVerilog code should include comments that explain how it works.

A screenshot of simulation results proving that your module functions correctly. Make sure that the screenshot's signal name and time labels are legible.

A written report that explains how your simulation results prove that that your module functions correctly.