Using the System Verilog conditional operator within one or more assign statements, write a module that shifts 8-bit input data [7:0] right logically by the number of positions specified by 3-bit input shift[2:0] ; the shifted result is available on 8- bit output shout [7:0] 1. Write a System Verilog testbench model that tests your shift module by applying all eight possible shift values. For each shift value apply two arbitrary data input values. Choose data values that make it easy to see that the result on shout is correctly shifted. 2