EXERCISES aX + Y for a vector length 100. Initially, R1 is set to 1) [30] The following code implements Y the base address of array X and R2 is set to the base address of Y DADDIU R4 ,R1, #800 ; RI -upper bound for foo: L.DF2,0(R1) ; (F2 ) -X() MUL.D F4, F2, FO (F4) ax(i) L.DF6 , 0 (R2) ; (F6) -Y(1) ADD . D F6, F4 , F6 ; (F6) = a"X (i) + Y(1) x DADDIU R1,R1,#8 ; increment X index DADDIU R2, R2,#8 ; increment Y index DSLTU R3,R1,R4 test: continue loop? BNEZ R3,fooloop if needed Assume the functional unit latencies as shown in the table below. Assume a one cydle delayed branch that resolves in the ID stage. Assume that results are fully bypassed Instruction producing result FP FP add FP FP add Integer operations andal Any Instruction using result FP ALU FP ALU FP store PP store Latency in clock cycles loads a) [15] Assume a single-issue pipeline. Show how the loop would look both unscheduled by the compiler and after compiler scheduling for both floating-point operation and branch delays, including any stalls or idle clock cycles. What is the execution time (irn cycles) per element of the result vector, Y, unscheduled and scheduled? b) [15] Assume a single-issue pipeline. Unroll the loop as many times as necessary to schedule it without any stalls, collapsing the loop overhead instructions. How many times must the loop be unrolled? Show the instruction schedule. What is the execution time per element of the result? EXERCISES aX + Y for a vector length 100. Initially, R1 is set to 1) [30] The following code implements Y the base address of array X and R2 is set to the base address of Y DADDIU R4 ,R1, #800 ; RI -upper bound for foo: L.DF2,0(R1) ; (F2 ) -X() MUL.D F4, F2, FO (F4) ax(i) L.DF6 , 0 (R2) ; (F6) -Y(1) ADD . D F6, F4 , F6 ; (F6) = a"X (i) + Y(1) x DADDIU R1,R1,#8 ; increment X index DADDIU R2, R2,#8 ; increment Y index DSLTU R3,R1,R4 test: continue loop? BNEZ R3,fooloop if needed Assume the functional unit latencies as shown in the table below. Assume a one cydle delayed branch that resolves in the ID stage. Assume that results are fully bypassed Instruction producing result FP FP add FP FP add Integer operations andal Any Instruction using result FP ALU FP ALU FP store PP store Latency in clock cycles loads a) [15] Assume a single-issue pipeline. Show how the loop would look both unscheduled by the compiler and after compiler scheduling for both floating-point operation and branch delays, including any stalls or idle clock cycles. What is the execution time (irn cycles) per element of the result vector, Y, unscheduled and scheduled? b) [15] Assume a single-issue pipeline. Unroll the loop as many times as necessary to schedule it without any stalls, collapsing the loop overhead instructions. How many times must the loop be unrolled? Show the instruction schedule. What is the execution time per element of the result