Exercises

P$6\mathrm{.}1.$ Considering Figure $6\mathrm{.}1,$ if the amount of time to perform a multplication was reduced by a factor of $2,$ draw the corresponding system, including any necessary buffers to maintain a pipeline balance.

P$6\mathrm{.}2.$ Draw the interface between two components where one is producing data and the second is consuming data. Be sure to follow the Kahn Process Network model.

P$6\mathrm{.}3.$ Describe the similarities and differences between synchronous and asynchronous design.

P$6\mathrm{.}4.$ Draw the interface for a FIFO. Compare this interface to that of a BRAM.

P$6\mathrm{.}5.$ Write the VHDL that will instantiate a BRAM and function like a FIFO. Include in this design a mechanism to report to the user the number of elements currently stored in the FIFO.

P$6\mathrm{.}6.$ Write an application that will use the Central DMA controller to read $512$ Bytes of data from DDR$2$ and write it to a hardware core. Assume data are stored at $00123000$ and must be written to $0B001000.$

P$6\mathrm{.}7.$ Compare the performance of a system that is operating in CMDA mode with that of a system running as a bus master that is able to access memory on its own.

P$6\mathrm{.}8.$ Implement a Native Port Interface design that will support direct memory access reads and writes to the MPMC without the aid of the processor.