Experiment $\backslash$#$12$

Design of Synchronous Counters

Objectives:

$1.$ Learn step by step design of a synchronous counter from a given state diagram using J$-$K Flip Flops.

$2.$ Design a non$-$sequential counter from a given state diagram.

Introduction:

You will design and build a synchronous counter using J$-$K Flip Flops. The desired states will be given, and you will be required to design the custom counter that meets the design specification. The required design process was explained in the weekly lecture.

Lab Report Requirements:

You must submit all work including state diagrams, next$-$state table, transition table, Karnaugh maps, derived expressions, and schematic drawing, be sure to answer the conclusion question. All work should be provided on this lab syllabus. You are also required to submit your Logisim $.$circ file so your instructor can run and test your circuit!

Part $1$

Objective $1$:

Given a state diagram, design a synchronous up counter. Follow the design steps outlined below in the procedure.

Materials Required:

Logisim Procedure $1$:

$1.$ State Diagram $-$ Given the following state diagram design a synchronous up counter.

$2.$ Next State Table $-$ Create the next state table from the information given in the state diagram.

Next State Table Procedure $1$:

$1.$ State Diagram $-$ Given the following state diagram design a synchronous up counter.

$2.$ Next State Table $-$ Create the next state table from the information given in the state diagram.

Next State Table Procedure $1$:

$1.$ State Diagram $-$ Given the following state diagram design a synchronous up counter.

$2.$ Next State Table $-$ Create the next state table from the information given in the state diagram.

Next State Table $3.$ J$-$K Flip Flop Transition Table $-$ Review the transition table for a J$-$K Flip Flop given below. $\backslash ($ Q$\_\{$N$\}\backslash )$ is the present state of the flip $-$ flop $($before a clock pulse$)$ and $\backslash ($ Q$\_\{$N$+1\}\backslash )$ is the next state $($after a clock pulse$).$ The J and K input values are those that will cause the listed transition to occur. X is a "Don't Care" value, which could be a $0$ or a $1.$

Transition Table for a J$-$K Flip Flop

$\backslash$begin$\{$tabular$\}\{|$ccc$|$cc$|\}$

$\backslash$hline $\backslash$multicolumn$\{2\}\{|$c$|\}\{$ Output Transitions $\}$ & $\backslash$multicolumn$\{2\}\{$c$|\}\{$ Flip$-$Flip Inputs $\}\backslash \backslash$

$\backslash (\backslash$mathrm$\{$Q$\}\_\{\backslash$mathrm$\{$N$\}\}\backslash )$ & & $\backslash (\backslash$mathrm$\{$Q$\}\_\{\backslash$mathrm$\{$N$\}+1\}\backslash )$ & J & K $\backslash \backslash$

$\backslash$hline $0$ & $\backslash (\backslash$square $\backslash )$ & $0$ & $0$ & X $\backslash \backslash$

$\backslash$hline $0$ & $\backslash (\backslash$square $\backslash )$ & $1$ & $1$ & X $\backslash \backslash$

$\backslash$hline $1$ & $\backslash (\backslash$square $\backslash )$ & $0$ & X & $1\backslash \backslash$

$\backslash$hline $1$ & $\backslash (\backslash$square $\backslash )$ & $1$ & X & $0\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}4.$ Karnaugh Map $-$ Plot K$-$Maps of the J and K inputs for each of the flip$-$flops in the counter. Each cell in the K$-$Map represents one of the present states in the counter sequence $($Refer to present state on Next$-$State Table$).$ Remember to plot the "Don't Cares" also!

$4.$ Group the $1\text{'}$s $-$ Group the $1\text{'}$s including as many "don't cares" as possible to maximize the simplification. Remember groups must include $\backslash (1,2,4,8\backslash$ldots $\backslash )$ cells. Groups must be indicated for credit. $5.$ Write the expression $-$ Write the expression for the J and K inputs.

$```$

J

K

J

K

J

K$2$

$```$

$6.$ Implementation of Circuit $-$ Using the expressions found above draw an implementation of the counter using J$-$K Flip Flops in Logisim $($Do NOT use Logisim Evolution!$).$ The expressions will define the connections to the J and K inputs of each JK Flip$-$Flip used. Be sure to account for any other input $($asynchronous inputs$/$enable if applicable$).$ Remember that you need to apply a clock input! You should connect an output pin to each Q output to monitor the operation of your circuit. When you draw your circuit be sure to arrange the Q output pins so they are presented with MSB on the left side and LSB on right side to make it easier to match your circuit outputs with the state machine diagram. You can review your work from Lab $10$ Latches and Flip Flops if you need to be reminded how to wire to a Flip$-$Flop and simulate the circuit manually. RESULTS $1$:

$1.$ Test the counter $-$ Repeatedly apply a clock pulse manually $($you need to Tick twice to apply the full clock pulse!$).$ Compare your circuit Q output pins to each of the required states as given in the state diagram. The order of each state should match the order in the given state diagram. If the output states and the order in which they appear do not each match the design requirements, you need to go back and troubleshoot your design process to find the source of the error.

Conclusion $1$:

Did your design perform the required function? Did the count outputs follow the given state diagram? Did any invalid counts appear? If so explain.